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M.N. Velev, and P. Gao,
Efficient SAT Techniques for Relative Encoding of Permutations with Constraints,
22nd Australasian Joint Conference on Artificial Intelligence (AI '09),
A. Nicholson, and X. Li, eds., LNAI 5866, Springer-Verlag, December 2009, pp. 517-527.
C39
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M.N. Velev, and P. Gao,
Efficient SAT-Based Techniques for Design of Experiments by Using Static Variable Ordering,
10th IEEE International Symposium on Quality Electronic Design (ISQED '09), March 2009, pp. 371-376.
C37
M.N. Velev, and P. Gao,
Comparison of Boolean Satisfiability Encodings on FPGA Detailed Routing Problems,
Design, Automation and Test in Europe (DATE '08), March 2008, pp. 1268-1273.
C36
M.N. Velev,
Exploiting Hierarchy and Structure to Efficiently Solve Graph Coloring as SAT,
26th IEEE/ACM International Conference on Computer-Aided Design (ICCAD '07), November 2007, pp. 135-142.
C35
M.N. Velev,
Using Abstraction for Efficient Formal Verification of Pipelined Processors with Value Prediction,
7th IEEE International Symposium on Quality Electronic Design (ISQED '06), March 2006, pp. 51-56. [Nominated for best paper award]
C34
M.N. Velev,
Formal Verification of Pipelined Microprocessors with Delayed Branches,
7th IEEE International Symposium on Quality Electronic Design (ISQED '06), March 2006, pp. 296-299.
C33
M.N. Velev,
Efficient Formal Verification of Pipelined Microprocessors,
International SoC Design Conference (ISOCC '05), October 2005, pp. 1-4. [Invited talk]
C32
M.N. Velev,
Automatic Formal Verification of Liveness for Pipelined Processors with Multicycle Functional Units,
13th Advanced Research Working Conference on Correct Hardware Design and Verification Methods (CHARME '05),
D. Borrione, and W.J. Paul, eds., LNCS 3725, Springer-Verlag, October 2005, pp. 97-113.
C31
M.N. Velev,
Comparison of Schemes for Encoding Unobservability in Translation to SAT,
Asia and South Pacific Design Automation Conference (ASP-DAC '05),
January 2005, pp. 1056-1059.
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M.N. Velev,
A New Correctness Proof for Positive Equality,
International Colloquium on Theoretical Aspects of Computing (ICTAC '04), September 2004, pp. 495-512.
C28
M.N. Velev,
A New Generation of ISCAS Benchmarks from Formal Verification of High-Level Microprocessors,
International Symposium on Circuits and Systems (ISCAS '04), Vol. 5, May 2004, pp. 213-216.
C27
M.N. Velev,
Encoding Global Unobservability for Efficient Translation to SAT,
7th International Conference on Theory and Applications of Satisfiability Testing (SAT '04), May 2004, pp. 197-204.
C26
M.N. Velev,
Efficient Formal Verification of Pipelined Processors with Instruction Queues,
Great Lakes Symposium on VLSI (GLSVLSI '04), April 2004, pp. 92-95.
C25
M.N. Velev,
Exploiting Signal Unobservability for Efficient Translation to CNF in Formal Verification of Microprocessors,
Design, Automation and Test in Europe (DATE '04), February 2004, pp. 266-271.
C24
M.N. Velev,
Using Positive Equality to Prove Liveness for Pipelined Microprocessors,
Asia and South Pacific Design Automation Conference (ASP-DAC '04), January 2004, pp. 316-321.
C23
M.N. Velev,
Efficient Translation of Boolean Formulas to CNF in Formal Verification of Microprocessors,
Asia and South Pacific Design Automation Conference (ASP-DAC '04), January 2004, pp. 310-315.
[One of four papers nominated for the 10th Anniversary Retrospective Most Influential Paper Award at ASP-DAC'14, based on the references reported by Google Scholar for all papers published at ASP-DAC'04]
C22
M.N. Velev,
Using Automatic Case Splits and Efficient CNF Translation to Guide a SAT-Solver When Formally Verifying Out-of-Order Processors,
Artificial Intelligence and Mathematics (AI&MATH '04), January 2004, pp. 242-254.
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M.N. Velev, and R.E. Bryant,
EVC: A Validity Checker for the Logic of Equality with Uninterpreted Functions
and Memories, Exploiting Positive Equality and Conservative Transformations,
Computer-Aided Verification (CAV '01),
G. Berry, H. Comon, and A. Finkel,
eds.,
LNCS 2102, Springer-Verlag,
July 2001, pp. 235-240.
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R.E. Bryant, S. German, and M.N. Velev,
Exploiting Positive Equality in a Logic of Equality with
Uninterpreted Functions,
Computer-Aided Verification (CAV '99), N. Halbwachs and D. Peled,
eds.,
LNCS 1633, Springer-Verlag,
July 1999, pp. 470-482.
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R.E. Bryant, S. German, and M.N. Velev,
Processor Verification Using Efficient Decision Procedures for a Logic of
Uninterpreted Functions,
Automated Reasoning with Analytic Tableaux and Related Methods (TABLEAUX '99),
N.V. Murray,
ed.,
LNAI 1617, Springer-Verlag,
June 1999, pp. 1-13.
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M.N. Velev, R.E. Bryant, and A. Jain,
Efficient Modeling of Memory Arrays in Symbolic Simulation,
Computer-Aided Verification (CAV '97), O. Grumberg,
ed.,
LNCS 1254, Springer-Verlag,
June 1997, pp. 388-399.